Digital devices are constantly becoming more pervasive in numerous applications, such as personal computers, telecommunications, consumer electronic devices, and the like. Consequently, the use of digital memories also constantly increases. As a result, it is imperative to improve reliability of digital memories so that devices using such memories are likewise reliable.
The reliability of an SRAM cell depends on many factors. As detailed below, one key factor is the voltage level applied to such a cell. In order to appreciate the effect of such a voltage level, it is first instructive to demonstrate the prior art application of voltage to an SRAM cell. Toward that end, FIG. 1 illustrates a typical SRAM cell 10 connected in a known "4T-2R" configuration, that is, an SRAM cell having four transistors and two pull-up resistors. Specifically, cell 10 includes two n-channel transistors 12 and 14 configured in a cross-connected fashion. The drain of transistor 12 is connected to a cell node 16 and the source of transistor 12 is connected to a cell node 18. The drain of transistor 14 is connected to a cell node 20 and the source of transistor 12 is connected to node 18. The gate of transistor 12 is connected to cell node 20 while the gate of transistor 14 is connected to cell node 16. Node 18 is connected to a low reference potential, denoted Vss, which is typically connected to ground.
Nodes 16 and 20 are referred to herein as cell nodes as readily used in the art. Node 16 is connected through a pull-up resistor 22 to a voltage source node 24, and node 20 is connected through a pull-up resistor 26 to voltage source node 24. Voltage source node 24 is connected to a system level voltage, denoted V.sub.cc, which is typically connected to a voltage on the order of 5 volts. V.sub.cc is referred to as a system level voltage because, as well known as in the art, it is the supply voltage typically connected to other areas of a chip containing memory cell 10, as well as other related circuitry such as decoders, buffers, and the like. Note that the resistance value of resistors 22 and 26 is the same (given whatever level of tolerance is associated with those resistors), and is typically on the order of 10.sup.10 to 10.sup.12 Ohms.
Each of cell nodes 16 and 20 are connected in like fashion to a corresponding bit line 28 and 30, respectively. Particularly, cell node 16 is connected through an n-channel transistor 32 to bit line 28, and cell node 20 is connected through an n-channel transistor 34 to bit line 30. For reasons stated below, transistors 32 and 34 are referred to herein as passgate transistors. The gates of passgate transistors 32 and 34 are connected to a write/read line 35 (i.e., word line) which, as described below, receives a write/read signal (denoted "W/R") at a voltage level equal to V.sub.cc to allow writing to, or reading from, SRAM cell 10.
Bit lines 28 and 30 are each connected at one end to load elements 28a and 30a, respectively. Load elements 28a and 30a are biased by the same system level voltage as voltage source node 24, that is, V.sub.cc. The voltage output by load elements 28a and 30a depends on the component selected as the load. Particularly, as known in the art, load elements 28a and 30a each typically consist of a single transistor. For example, each load element 28a and 30a may include a p-channel transistor with its source connected to V.sub.cc, its gate to V.sub.ss, and its drain connected to the respective bit line. In this instance, the drain voltage of the p-channel transistor would output a bias of V.sub.cc to the respective bit line. As a second example, each load element 28a and 30a may include an n-channel transistor with its gate and drain connected to V.sub.cc, and its source connected to the respective bit line. In this instance, the source voltage of the n-channel transistor would output a bias of V.sub.cc -V.sub.Tnload to the respective bit line, where V.sub.Tnload is the threshold voltage of the n-channel transistor of load elements 28a and 30a. Because of these alternative voltage levels on bit lines 28 and 30, FIG. 1 illustrates the potential from each load as "V.sub.cc OR V.sub.Tnload ".
At their other ends, bit lines 28 and 30 are each connected to circuitry (not shown), such as a driver/sense amplifier, for writing and reading a data bit to and from each of the bit lines. As known in the art, for a given memory cell, the signals along bit lines 28 and 30 are logically complementary. Consequently, for purposes of illustration in FIG. 1, bit line 28 is shown with a signal BIT while bit line 30 is shown with a signal BIT, that is, the logical complement of BIT.
The operation of writing to cell 10 is as follows. Initially, logically complementary signals are connected to bit lines 28 and 30. These signals are typically accomplished using known pre-charging techniques. For example, if bit line 28 is to be logically high while bit line 30 is to be logically low, bit line 28 is allowed to fully pre-charge to V.sub.cc if a p-channel transistor is used within load 28 (or V.sub.cc -V.sub.Tnload if an n-channel transistor is used within load 28), while bit line 30 is discharged. Next, W/R is asserted at V.sub.cc so that transistors 32 and 34 couple bit lines 28 and 30 to pull up, or pull down, nodes 16 and 20, respectively. Thus, transistors 32 and 34 act as gates which, when enabled, pass the data from bit lines 28 and 30 to transistors 16 and 20; therefore, transistors 32 and 34 are referred to herein as passgate transistors. Once the high from bit line 28 is coupled to cell node 16 and further to the gate of transistor 14, transistor 14 conducts. At the same time, the low from bit line 30 is coupled to cell node 20 and further to the gate of transistor 12, thereby keeping transistor 12 from conducting. Next, W/R is de-asserted. Because transistor 14 is now conducting, it will maintain a low potential at cell node 20 and, therefore, maintain transistor 12 in a nonconducting fashion. In addition, because transistor 12 is not conducting, and given the resistance size of resistor 22, the system level voltage V.sub.cc will continuously pull up cell node 16 to V.sub.cc. Again, this voltage at cell node 16 connects to the gate of transistor 14 and, thus, maintains transistor 14 in a conducting fashion.
Given the above, one skilled in the art will recognize that, once passgate transistors 32 and 34 no longer conduct, the states of transistor 12 and 14 remain the same as caused by the complementary signals received from bit lines 28 and 30. Further, if the example were reversed (i.e., bit line 28 low while bit line 30 high), then the states of transistors 12 and 14 also would reverse, but again would remain static once passgate transistors 32 and 34 no longer conduct.
Having discussed a typical SRAM cell, recall from above that one key factor affecting SRAM cell reliability is the voltage level applied to such a cell. In the example of FIG. 1, this is the voltage level applied at voltage source node 24 which, in the prior art, is V.sub.cc. In particular, it is known in the art that the transistors of SRAM cell 10 are commonly constructed with fairly thin interlevel oxides, that is, oxide layers between various layers or components, such as the gate oxide which separates the transistor gate from the underlying semiconductor, or other oxides between component layers. It is further known that such thin interlevel oxides are likely to degrade over time, particularly at high voltage levels. Consequently, one way to improve SRAM cell reliability over time is to lower voltages applied to the memory cell transistors. Because of this principle, in some prior art systems V.sub.cc has been reduced globally, that is, all nodes connected to V.sub.cc receive a lesser voltage potential. Thus, in FIG. 1, the voltage at voltage source node 24 would be reduced, as would the voltages on both loads 28a and 30a. By reducing the voltage in such a global manner, the life span of the SRAM cell is improved.
Unfortunately, the present invention recognizes that many memories or memory cell applications do not permit global reduction of V.sub.cc. Further, a global reduction of V.sub.cc beyond a certain level may cause inaccurate operation and performance degradation. Therefore, it is an object of the present invention to provide an improved memory which operates with a non-reduced system level voltage of V.sub.cc, while lowering the voltage internal to the cell to a value less than V.sub.cc. By doing this, the memory has improved reliability with no performance degradation.
It is a further object of the present invention to provide such an improved memory having a greater reliability over prior art SRAM memory cells.
It is a further object of the present invention to provide such an improved memory which may be configured as a 4T-2R cell, 6-T cell, or other SRAM memory configuration benefitting from a reduced cell voltage.
It is a further object of the present invention to provide such an improved memory having a biasing circuit for producing a reduced cell voltage which is easily and efficiently included within the memory.
Still other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having references to the following specification together with its drawings.